There is a semiconductor device for transmitting/receiving a data signal by wireless communication such as a wireless tag (also called an IC tag, an IC chip, an RF (Radio Frequency) tag, an RFID (Radio Frequency Identification) tag, an electronic tag, or a transponder). In a device for transmitting/receiving a data signal, cyclic redundancy checking (CRC) is performed for checking whether the data signal is transmitted accurately. In the cyclic redundancy checking, a polynomial (called a code polynomial) in which each bit of a received data signal is set as a coefficient is divided by a predetermined generator polynomial, and a coefficient of a remainder polynomial (hereinafter called a CRC code) is calculated. The CRC code is compared to a predetermined signal so that it is determined whether the received data signal is correct.
As for a circuit for performing cyclic redundancy checking (a cyclic redundancy check circuit), a structure having a plurality of delay elements and a plurality of exclusive OR circuits is proposed (Reference 1: Japanese Patent Application Laid-Open No. Hei 10-107650).
The structure of the cyclic redundancy check circuit is described with reference to FIG. 12. In FIG. 12, a cyclic redundancy check circuit includes delay elements S0 to S15 and exclusive OR circuits EXOR 0 to EXOR 2 which calculate an exclusive OR of two inputted signals.
The delay elements S0 to S4 sequentially output a signal which is shifted, in synchronization with a clock signal 181. That is, the delay elements S0 to S4 form a first shift register (denoted by SR 1 in FIG. 12). The delay elements S5 to S11 sequentially output a signal which is shifted, in synchronization with the clock signal 181. That is, the delay elements S5 to S11 form a second shift register (denoted by SR 2 in FIG. 12). The delay elements S12 to S15 also sequentially output a signal which is shifted, in synchronization with the clock signal 181. That is, the delay elements S12 to S15 form a third shift register (denoted by SR 3 in FIG. 12). An output of the exclusive OR circuit EXOR 0 is inputted to the delay element S0 of the first shift register SR 1. An output of S4 of the first shift register and the output of the exclusive OR circuit EXOR 0 are inputted to the exclusive OR circuit EXOR 1. An output of the exclusive OR circuit EXOR 1 is inputted to S5 of the second shift register. An output of S11 of the second shift register and the output of the exclusive OR circuit EXOR 0 are inputted to the exclusive OR circuit EXOR 2. An output of the exclusive OR circuit EXOR 2 is inputted to S12 of the third shift register. A data signal 182 and an output of S15 of the third shift register are inputted to the exclusive OR circuit EXOR 0.
The cyclic redundancy check circuit having the aforementioned structure calculates a 16-bit CRC code corresponding to the inputted data signal 182, and outputs the CRC code from out_1 to out_16 in parallel.